Chapter 1: Gold-Based Surface Micromachining Process

Introduction

The UW-MEMS process is a research-oriented, cost effective, proof of concept, multi-user microfabrication process for industries, universities and government agencies offered at the University of Waterloo, Waterloo, Ontario, Canada. The process is gold-based surface micromachining derived and developed from work carried out by the Center for Integrated RF Engineering (CIRFE) at the University of Waterloo over the past years. It has been used successfully to build several MEMS devices [1]-[8].

The following is a general description and user guide for the UW-MEMS process which is optimized for many RF applications, such as contact and capacitive MEMS switches, electrostatic varactors, phase shifters, tunable filters and impedance matching networks as well as RF passives including transmission line circuits, planar inductors, interdigital and metal-insulator-metal (MIM) capacitors and resistive lines. Nevertheless, the process is also applicable to many other MEMS devices, such as micro-mirror devices and surface micromachined inertial sensors. Accordingly, designers from all micro-scale engineering disciplines are encouraged to submit their designs.

The guidelines in this handbook target users with a minimum of processing experience. The design rules of UW-MEMS are detailed in chapter 2. Moreover, a detailed example is provided in chapter 3 to illustrate the typical layouts that designers need to submit for UW-MEMS.

Process Overview

The UW-MEMS microfabrication process employs only seven masks, and it starts with a 0.025” thick Alumina substrate polished on both sides with a relative permittivity of 9.9 and loss tangent of 0.0001 at 1MHz. 

The seven masks used for the entire fabrication are electron-beam-write chromium masks that are produced from nine layout layers, which are detailed in the chapter 2. Up to this stage, it is worth noting that more than one layer can be used to produce ONLY one mask. This fact is implied in the second and seventh main steps shown below.

 

Layer #1: Titanium Tungsten Bias Lines

After the RCA cleaning of the wafer, 50 nm TiW layer is sputtered and patterned using the layer “TiW”.

 After patterning using Layer “TiW” Figure1.1: After patterning using Layer “TiW”

 

Layers #2 and #3: First Dielectric

A 0.7 mm SiO2 is deposited at 250⁰C by plasma enhanced chemical vapor deposition (PECVD) and patterned using reactive ion etching (RIE). RIE is then used to strip away the etch-mask photoresist. The pattern is formed using a single mask based on the layout layers “D1” and “D1HOLE” combined.

 After patterning using Layers “D1” & “D1HOLE” Figure1.2: After patterning using Layers “D1” & “D1HOLE”

 

Layer #4: First Gold

An evaporated 40nm Cr/70nm Au bilayer is deposited as a seed layer. A negative photoresist (PR) mold is patterned by photolithography using layer “G1” and 1µm Au is electroplated inside that mold. The mold and the seed layer are removed afterwards. Cr serves no more than an adhesion layer for Au.

 After patterning using Layer “G1” Figure1.3: After patterning using Layer “G1” 

 

Layer #5: Second Dielectric

A 30nm of TiW is sputtered followed by the deposition of 0.7µm SiO2 PECVD at 250˚C. The SiO2 and TiW layers are then dry etched in RIE in order to pattern them using “D2” layer.  TiW layer serves here as an adhesion layer between SiO2 and Au.

 After patterning using Layer “D2”Figure1.4: After patterning using Layer “D2”

 

Layer #6: Anchor Openings

Spin coated Polyimide is used as the sacrificial layer for the Au structural layer in UW-MEMS. Initially, it is coated to a thickness of 2.5µm; then, it is patterned by “A” layer in RIE in order to etch the polyimide and fully open the anchor holes.

 After patterning using Layer “A”Figure1.5: After patterning using Layer “A”

 

Layer #7: Dimple Openings

Similar to anchor patterning, the dimples openings are performed in polyimide using an RIE etching step using the pattern of “D” layer. The depth of the etching is set to be 1mm.

 After patterning using Layer “D”Figure1.6: After patterning using Layer “D”

 

Layers #8 and #9: Second Gold

The second Au layer consists of sputtered 70nm Au seed layer and an electroplated Au layer.  The total thickness of Au is set to be 2µm, and it is used as the structural layer for all the MEMS devices. A negative PR mold is used to pattern this layer based on the layout layers “G2” and “G2R” combined appropriately.

 After patterning using Layers “G2” and “G2R”Figure1.7: After patterning using Layers “G2” and “G2R”

Final Release Step

Before releasing the devices, the wafers are diced into individual dies according to the dicing lines in the layout. The sacrificial layer is then removed in O2 plasma dry etching in RIE. At this stage, the microfabrication of UW-MEMS devices is complete and the samples are packaged for shipping to the customers.

 After releasing the device by stripping away all polyimide Figure1.8: After releasing the device by stripping away all polyimide