Chapter 2: UW-MEMS Layout Design Guidelines

Design Rules: General Outlines

The layout design rules for the UW-MEMS process are explained in the following tables and illustrated in schematic format following the tables. First, Table 1 outlines the different layer names, corresponding material thicknesses as well as layer numbers and description.

Table 1: Layer Names, Material Thicknesses, Layers Order, Layer Description and Comments

Table 2 outlines the layers that are used during the microfabrication process.  Please note that for the case of “Light Filed”, you draw the features that you want to be remained on the wafer.  For example, for TiW layer patterning, you draw the features or traces such as bias lines. For the “Dark Field”, you draw the parts you want to be removed from the corresponding layer such as release holes or openings for anchors and dimples.  Please pay special attention to this concept. Failure to do so will result in a reverse polarity devices.

In other words, for D1HOLE and G2R, you draw only the location of dielectric openings and release holes in gold, respectively. These layers will be subtracted from the D1 and G2 layers by CIRFE personnel prior to printing the second and seventh lithographic masks.

Table 2: Layer Names, Layer Polarity Type and Comments

Table 3 presents the lithographic mask numbers with the respective GDSII indices of their constituting layout layers. GDSII is the only format that UW-MEMS accept from all users.  Please use the GDSII numbers that are specified in the table for each layout layer to avoid confusion. Layers D1HOLE and G2R are just employed to create the openings in the D1 layer and the release holes in G2 layer, respectively. No lithographic masks are printed specifically for these layers. Please note that the dimples are meant for small features.  Nominal surface area is 10µm by 10µm. However, they can be used for long lines, but it is recommended that the width of the lines be 10µm.

Table 3: UW-MEMS Masks and GDSII Layer Indices

Design Rules: Overlaps & Enclosures

Generally, the following guidelines should be considered:

• For overlaps and enclosures of the layers, up to 10mm of misalignment between the layers is assumed. This is due to the limitations of our photolithography system. This is an advisory design rule.
• TiW lines are designated for the DC bias lines with no current flow.  This layer is very thin, and it is not intended for power transfer.

The following outlines the specific layout design rules to which close attention must be paid. It is worth emphasizing that the minimum feature size and minimum spacing between features are limits to which the designers should strictly adhere. Ideally, adding a 10mm additional safety margin to these numbers may increase the yield of fabrication. Users can have round, orthogonal or any arbitrary shape in your layout. The release holes must be 10mm x 10mm squares with edge to edge distances not exceeding 20µm. Please do not use this layer to define geometries. The features are embedded to provide access to underneath the structural layer during the release purposes.

1.    “TiW” resistive DC bias lines:

Description	Rule Label	Value (µm)
Width/Length of TiW	TiW1	≥ 10
Spacing of TiW	TiW2	≥ 10

2.    First Dielectric “D1” stacked with “TiW” and Gold “G1”:

Description	Rule Label	Value (µm)
Extension of TiW from D1	TiW3	≥ 20
Width/Length of D1	D11	≥ 15
Spacing of D1	D12	≥ 15
Overlap of D1 with TiW	D13	≥ 5
Extension of D1HOLE from TiW	D14	≥ 10
Width/Length of D1HOLE	D15	≥ 35
Overlap of G1 pad with TiW or D1	G13	≥ 15
Overlap of G1 pad with TiW	G14	≥ 10

  Note: TiW lines MUST be always covered with D1, G1, or both.

3.    First Gold “G1”:

Description	Rule Label	Value (µm)
Width/Length of G1	G11	≥ 10
Spacing of G1	G12	≥ 10

4. Second Dielectric “D2” on top of TiW adhesion layer:

Description	Rule Label	Value (µm)
Width/Length of D2	D21	≥ 15
Spacing of D2	D22	≥ 15
Overlap of D2 with G1	D23	≥ 10
Overlap of D2 with A	D24	≥ 15
Spacing of D2 from G1	D25	≥ 15
Feature size of A over D2	AD	≤ 200

Note: D2 over 2 separated trances MUST be separated.

Note: Anchor on top of D2 cannot be used as mechanical support but can be used for Metal-Insulator-Metal (MIM) capacitor.

5. Anchor “A” Openings:

Description	Rule Label	Value (µm)
Width/Length of A	A1	≥ 10
Spacing of A	A2	≥ 10
Overlap of G1 with A (A MUST be covered with G1)	A3	≥10
Overlap of G2 with A (A MUST be covered with G2)	A4	≥ 5
Spacing of D2 from A	A5	≥ 10

6. Dimple “D” Openings:

Description	Rule Label	Value (µm)
Width/Length of D	DIM1	≥ 10
Spacing of D	DIM2	≥ 10
Overlap of G2 with D	DIM3	≥ 5
Overlap of G1 with D	DIM4	≥ 5

7. Second Gold “G2”:

Description	Rule Label	Value (µm)
Width/Length of G2	G21	≥ 10
Spacing of G2	G22	≥ 10
Ratio of G23/G21 when G2 is not anchored to G1	G23/G21	≤ 30
Non-anchored length of G2	G23	≤ 1200
Width/Length of G2R	G24	≥ 10
Spacing of G2R (edge-to-edge)	G25	≥ 20
Spacing of G2R from G2 edge	G26	≥ 10
Spacing of G2R from A	G27	≥ 10 &  ≤ 30

8. Caution 1:

Note: This configuration results in short-circuit between the two G1 traces due to the conductive TiW thin layer underneath the D2 layer.

9. Caution 2:

Note: This configuration may result in short-circuit between the G1 and G2 traces through D2 layer.

Material Properties

Table 4 reports some of the mechanical and electrical properties of the UW-MEMS process. The data is based on the measurements performed on earlier UW-MEMS processes and agree well with the nominal known values in the literature. Designers can use the existing values in the literature for the other material properties.

Table 4: Physical properties of UW-MEMS materials

Material	Residual Stress (MPa)	Conductivity (Ω-1/m)	Sheet Resistance (Ω/□)	Relative Permittivity
TiW of Resistive Bias Lines	------	------	20*	------
SiO2 of D1 and D2	------	------	------	4
Au of G1 and G2	190 +/- 30%  Tensile	3.6х107	------	------

^*Higher resistivity (500Ω/□) will be optionally available.