Candidate
Gangqiang Yang
Title
Hardware implementations and optimizations of the Warbler pseudorandom number generator
Supervisors
Guang Gong and Mark Aagaard
Abstract
Pseudorandom number generators (PRNGs) are a critical component for the EPC Class 1 Generation 2 Radio Frequency Identification (RFID) system, which is regarded as a promising technology for the Internet of Things era. A PRNG is able to provide random numbers for anti-collision mechanism, providing reader identity verification, masking the data, and constructing mutual authentication protocols. In this talk, we investigate efficient hardware implementations and optimizations of the lightweight Warbler PRNG, and demonstrate that Warbler meets the area and power consumption requirements for passive RFID systems. Warbler is built upon three nonlinear feedback shift registers (NLFSRs) and four WG-5 transformation modules. We employ two design options to implement Warbler and three different compilation methods to further optimize the area, maximum operating frequency, and power consumption. Our results of Warbler with throughput of 1 bit per five clock cycles (1/5 bpc) outperform that of most of the lightweight primitives. More importantly, we improve the throughput from 1/5 bpc to 1 bpc by increasing 36% of the area and 0.218 µW and 4.337 µW at 100KHz and 2 MHz respectively of the total power consumption in CMOS 130nm, and by increasing 46% of the area in CMOS 65nm with the total power consumption increased by 0.452 µW and 2.845 µW at 100 KHz and 2 MHz respectively. In addition, we show that the areas of WG-5 transformation look-up tables depend on the specific decimation values.