ECE 730 Topic 16 - Spring 2016

ECE 730 Topic 16 - Embedded Semiconductor Memories

Instructor

Professor Manoj Sachdev

Calendar description

Static and dynamic behavior of MOS transistor short channel effects and scaling trends. Memory architectures and building blocks. SRAM, DRAM, and CAM cell design and analysis. Low- power, low-voltage circuit techniques. Memory yield, redundancy and reliability issues.

Prerequisite: ECE 445

Detailed description
Lecture topics Number of lectures
MOS Transistor Review
  • Static behavior
  • Parasitic capacitances and dynamic behavior
  • Short channel effects
  • Scaling concept
2
Static Random Access Memory Circuits
  • Architecture and building blocks
  • SRAM cell designs and analysis
  • Peripheral circuits - address decoders, sense amplifiers, precharge & equalize
  • Timing and control
  • Low-power, Low-voltage SRAMs
12
Dynamic Random Access Memory Circuits
  • Architecture and building blocks
  • DRAM circuits – cells, sense amplifiers, etc.
  • Timing and control
6
Content Addressable Memory Circuits
  • Architecture and building blocks
  • CAM cell design
  • Peripheral circuits – matchline sensing, Priority encoder
6
Memory Yield, Redundancy and Reliability
  • Defects in manufacturing
  • Memory fault models and test algorithms
  • Redundancy and Repair
  • Soft errors
  • Yield Models
10

Total lecture hours: 36

References

  1. K. Itoh, “VLSI Memory Chip Design,” Springer, 2001, ISBN 3-540-67820-4
  2. J. Rabaey et. al., “Digital Integrated Circuits: A Design Perspective, 2nd edition, Printice Hall, 2003, ISBN 0-13-090996-3
  3. Lecture Notes

Project

An individual project is an essential component of this course.