ECE 627 - Register-transfer-level Digital Systems
Instructor
Mark
Aagaard
Room:
EIT-4138
Email:
maagaard@uwaterloo.ca
Lectures
Wednesdays 8:30am-11:20am, EIT-3141
Prerequisites
Undergraduate course on digital hardware design with VHDL or Verilog.
Description
This course covers the design and analysis of digital-hardware systems at the register-transfer level. In terms of the level of abstraction at which we will work, this course is positioned above ECE-637: Design of VLSI MOS Integrated Circuits and below ECE-621: Computer Organization. The course will cover the complete design flow: from transforming a sequential algorithm into hardware through functional verification, timing analysis, power analysis, and faults and testability. The primary focus will be on implementing a system on an ASIC, but some attention will also be paid to FPGA-based implementations.
Course Outline
Textbook
Course notes: Register-transfer-level engineering by Mark Aagaard, to be distributed during the term.
Grading
| Midterm | 20% |
|---|---|
| Project | 30% |
| Final exam | 50% |
Project
The project will be the design, implementation, and optimization of a digital system for an ASIC. The optimization metrics will be: power, area, and performance. The tool suite will be Synopsys Design Compiler for logic synthesis, Synopsys IC-Compiler for physical synthesis, and Mentor Graphics Modelsim for simulation. The implementation technology will be an ASIC library created by Synopsys for educational purposes.
The projects will be run on the VLSI-linux computers. If you do not have an account on these computers, one will be created for you at the start of term. If your research group has the CMC tools installed on its own computers, you may use your research group's computers. The EDA software provided by CMC must be run only on ECE computers.
- VHDL syntax and semantics
- Modelling concurrent hardware
- Register-transfer-level modeling, design, and implementation
-
Optimizations
for
performance
and
area
- Pipelining
- Retiming
- Multiple clock domains
- Functional verification
-
Timing
analysis
and
modeling
- Critical paths and false paths
- Elmore delay model
- Logical effort delay model
-
Power
analysis
and
optimization
- Modeling power consumption
- Clock gating
- Operand gating
- Power reduction in FPGAs and ASICs
-
Faults
and
testing
- Test generation algorithms (D, PODEM)
- Scan testing
- Built-in self-test (BIST)
- Introduction to Galois-fields and BIST