ECE 621 - Computer Organization


Andrew Morton
Office: EIT 4015
Office hours: By appointment.

Course schedule

Wednesdays, 11:30 - 12:20 in room E5 5106.

Course description

This is a graduate course on computer architecture focusing on quantitative methods for cost and performance design trade‐offs. This course covers the fundamentals of classical and modern general processor design. This includes organization, performance, instruction‐sets, pipelining, caches, virtual memory, I/O, superscalar, out‐of‐order execution, speculative execution, multithreaded processors, multiprocessors, cache coherency, memory consistency and synchronization techniques; and special‐ purpose architectures.

Course website

The course website is on LEARN.  This website be used for posting projects, lecture notes and grades.


  • [Recommended] Dubois, Annavaram and Stenstrom, Parallel Computer Organization and Design, Cambridge University Press, 2012 (available from the bookstore)
    - On 3‐hour loan at Davis Center reserve desk: call# QA76.5 .D754 2012
  • [Alternative] Hennessy and Patterson, Computer Architecture: A Quantitative Approach, 5th edition, Morgan Kaufmann 2012.
    - On 3‐hour reserve in DC library. Call number: QA76.9.A73 P377 2012

Course prerequisites

There are no formal course requirements; however, students are expected to be familiar with the basics of instruction‐set architectures, assembly language programming, pipelines and caches.

Course objectives

At the end of this course you should be able to:

  • Describe the operation and scheduling of statically‐scheduled scalar pipelines, VLIW pipelines and dynamically‐scheduled superscalar pipelines.
  • Design and simulate a statically‐scheduled scalar pipeline using a Hardware Description Language.
  • Describe techniques that enable thread‐level parallel execution.

Topic list

  • SystemVerilog: gate‐level, dataflow and behavioural design
  • Instruction‐set architecture, RISC, CISC, exception handling
  • Technology trends, Flynn’s Taxonomy
  • Scalar pipeline structure, local and global scheduling, performance
  • VLIW pipeline structure, local and global scheduling, speculative loads, deferred exceptions, predicated execution
  • Dynamically‐scheduled superscalar pipeline structure, register renaming, physical register file, speculative loads, data prefetching, branch prediction, speculative execution
  • Thread‐parallel execution, locks, cache‐coherency, transactional memory, memory consistency, multi‐threaded processors
  • Data‐parallel architectures: GPUs and Many‐Core

Lecture notes

  • Will be done on the board
  • Will be posted on (typically after lecture)

Grading scheme

  • Project: 25%
  • Term paper: 25%
  • Final exam: 50%

Late submissions lose 25% per day. Assignments and deliverables not submitted receive a grade of 0. Regrading requests should be made within two weeks of return of the graded item. Any unclaimed paper submissions will be shredded one month after the term ends.


Design a cycle‐accurate implementation of a pipelined MIPS processor. Projects will be implemented in SystemVerilog and simulated with ModelSim. There will be several project deliverables during the first 8 weeks of term. The project will be done in groups of 2 students.

Term paper

The term paper is required to be a literature review of a current computer architecture topic. Topic selection is left to the student but must be approved by the instructor. The paper should be 5‐8 pages in the IEEE Transactions format. The paper will be due in the last week of lecture and may have an earlier deliverable.

University policies

  • Academic integrity: In order to maintain a culture of academic integrity, members of the University of Waterloo community are expected to promote honesty, trust, fairness, respect and responsibility.
  • Grievance: A student who believes that a decision affecting some aspect of his/her university life has been unfair or unreasonable may have grounds for initiating a grievance. Read Policy 70, Student Petitions and Grievances, Section 4. When in doubt please be certain to contact the department’s administrative assistant who will provide further assistance.
  • Discipline: A student is expected to know what constitutes academic integrity to avoid committing an academic offence, and to take responsibility for his/her actions. A student who is unsure whether an action constitutes an offence, or who needs help in learning how to avoid offences (e.g., plagiarism, cheating) or about “rules” for group work/collaboration should seek guidance from the course instructor, academic advisor, or the undergraduate Associate Dean. For information on categories of offences and types of penalties, students should refer to Policy 71, Student Discipline. For typical penalties check Guidelines for the Assessment of Penalties.
  • Appeals: A decision made or penalty imposed under Policy 70 (Student Petitions and Grievances) (other than a petition) or Policy 71 (Student Discipline) may be appealed if there is a ground. A student who believes he/she has a ground for an appeal should refer to Policy 72 (Student Appeals).
  • Note for students with disabilities: The AccessAbility Services, located in Needles Hall, Room 1132, collaborates with all academic departments to arrange appropriate accommodations for students with disabilities without compromising the academic integrity of the curriculum. If you require academic accommodations to lessen the impact of your disability, please register with the AccessAbility Services at the beginning of each academic term.