Thursday, August 1, 2013 — 4:00 PM EDT

Speaker

Amreen Khan

Title

High Efficiency Two-Stage GaN Power Amplifier with Improved Linearity

Abstract

The tradeoff between linearity and efficiency is the limiting point wideband power amplifier design. The wireless research focuses a lot its effort on building power amplifiers with these two criteria going hand in hand to build an optimal design.

This thesis investigates the various sources of nonlinearity associated with GaN HEMT transistors and their effects on the linearity metrics of power amplifiers. The investigation is based on the analysis of these sources of nonlinearity, a design based approach to mitigate them and compare to existing trends in power amplifier design. The device technology used in this design is CREE GaN HEMT transistors (45W and 6W).
In this report, a systematic approach to designing a two stage power amplifier is discussed and analyzed for design of linear and highly efficient power amplifier for base stations. The power amplifier consists of two stages, the driver stage and the power stage. The driver stage aims to linearize the power stage using circuit analysis and transistor properties along with providing the necessary gain. The power stage is built to compliment the driver stage and to achieve high efficiency of the power amplifier. The inter-stage matching network between the two stages achieves the required matching of impedances and the transmission lines in the bias feed control the harmonic impedances for optimal performance without disrupting performance at fundamental frequencies. This effectively improves and maintains high efficiency over 200MHz of bandwidth.

The design approach is simulated and fabricated to test the feasibility of a linear power amplifier operation with the use of DPD. The fabricated prototype achieves about 70% peak efficiency over the bandwidth and maintains linearity of above 40dBc ACLR and below 3% EVM. The measurement results indicated that the need for DPD is eliminated back-off at the center frequency (800MHz). The thesis presents a detailed comparison of the prototyped design with the existing multistage designs with linear driver. The report completes with conclusions drawn from measurements and the bandwidth limitations faced through the course of the design. Lastly, the possible future work is discussed that may allow to overcome the limitations of the design.

Supervisor

Professor Slim Boumaiza

Location 
E5 building
Room 4106/4128

,

S M T W T F S
26
27
28
29
30
31
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
1
2
3
4
5
  1. 2020 (171)
    1. September (1)
    2. August (9)
    3. July (32)
    4. June (29)
    5. May (32)
    6. April (27)
    7. March (13)
    8. February (20)
    9. January (16)
  2. 2019 (282)
    1. December (16)
    2. November (32)
    3. October (19)
    4. September (26)
    5. August (26)
    6. July (40)
    7. June (24)
    8. May (23)
    9. April (35)
    10. March (25)
    11. February (9)
    12. January (10)
  3. 2018 (150)
  4. 2017 (212)
  5. 2016 (242)
  6. 2015 (242)
  7. 2014 (268)
  8. 2013 (192)
  9. 2012 (31)