MASc Seminar: A Comparative Analysis for Low-voltage, Low-power, and Low-energy Flip-flops

Thursday, July 23, 2020 3:00 pm - 3:00 pm EDT

Candidate: Yugal Kishore Maheshwari

Title: A Comparative Analysis for Low-voltage, Low-power, and Low-energy Flip-flops

Date: July 23, 2020

Time: 3:00 PM

Place: Remote attendance

Supervisor(s): Sachdev, Manoj - Wright, Derek



Recently, several flip-flops have been proposed to increase their speed while reducing their power and energy consumption.

Flip-flop power is dependent on data activity and in many applications data activity is between 5-15%. In such cases, significantly large clock power and energy is wasted. This thesis explores performance of seven advanced D Flip-Flops in terms of power, delay, and energy using 65nm CMOS process technology. The main objective of this research is to compare and contrast recent flip-flops under different voltage and data activity conditions, and draw conclusions. 


Transmission gate flip-flop (TGFF) is used as a reference flip-flop, and based on comparison result TGFF has shown power-performance trade-offs. 18-T Single Phase Static Flip-Flop (18TSPC, TSPC18), and Low-power at low data activity (LLFF) are the fastest alternatives suitable for higher performance. However, LLFF consumes more power on higher data activities, where as

TSPC18 and 18TSPC consume more power on lower data activities. For lower data activities TCFF is power efficient amongst all, but poor in performance. Furthermore, post-layout simulation result illustrates that LLFF is energy efficient amongst all up to 20% of data activities, and 18TSPC is energy efficient for rest of higher data activities.