Wednesday, November 23, 2016 — 10:00 AM EST

Candidate

Danlu Guo

Title

A Comprehensive Study of DRAM Controllers in Real-Time Systems

Supervisor

Rodolfo Pellizzoni

Abstract

The DRAM main memory is a critical component and a performance bottleneck of almost all computing systems. Since the DRAM is a shared memory resource on multi-core platforms, all cores contend for the memory bandwidth. Therefore, there is a keen interest in the real-time community to design predictable DRAM controllers to provide a low memory access latency bound to meet the strict timing requirement of real-time applications.

An extensible cycle-accurate DRAM controller simulation framework is developed to simplify the process of validating new DRAM controller designs. With the help of the framework, a comprehensive evaluation of state-of-the-art predictable DRAM controllers is performed analytically and experimentally to show the impact of different system parameters. At last, a novel controller is proposed to provide a configurable trade-off between latency bound and bandwidth in mixed-critical systems.

Location 
E5 - Engineering 5
Room 4047
200 University Avenue West

Waterloo, ON N2L 3G1
Canada

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