Power Characterization of a Digit-Online FPGA Implementation of a Low-Density Parity-Check Decoder for WiMAX Applications
Low-Density Parity-Check (LDPC) Codes are a class of easily decodable error-correcting codes. Published bit-parallel LDPC decoders demonstrate high throughput and low energy-per-bit but require a lot of silicon area. Decoders based on digit-online arithmetic (processing several bits per fundamental operation) process messages in a digit-serial fashion, reducing the area requirements, and can process multiple frames in frame-interlaced fashion. Implementations on FPGA (Field Programmable Gate Array) are usually power- and area-hungry, but provide flexibility compared with application-specific integrated circuit implementations. With the penetration of mobile devices in the electronics industry the power considerations have become increasingly important. The power consumption of a Digit-Online decoder depends on various factors, like input Log-Likelihood Ratio (LLR) Bit Precision, Signal- to- Noise Ratio (SNR) and number of maximum number of iterations.
We implement our system on an Altera Stratix IV GX EP4SGX230 FPGA which comes on an Altera DE4 Development and Education Board. In this work, both bit-parallel and digit-online block LDPC decoder implementations on FPGAs for WiMAX 576-bit -rate-3/4 codes are studied, and power measurements from the DE4 board are reported. Various components of the system include a Random Data Generator, WiMAX Encoder, Multi-In Multi-Out (MIMO), Additive White Gaussian Noise (AWGN) generator, Channel LLR Buffer, WiMAX Decoder and Bit-Error Rate Calculator. The random data generator outputs pseudo-random bit patterns through an implemented Linear Feedback Shift Register (LFSR).
We synthesize Digit-Online Decoders with LLR precisions ranging from 6 bits to 13 bits and Bit-Parallel Decoders ranging from 3 bit LLR precision to 6 bits in Stratix IV FPGA. We exploit the fact that Digit-Online decoders can be clocked at higher frequency for higher LLR precisions. A 13-bit LLR Digit-Online Decoder can be used to decode in frame interlaced mode, two 6-bit LLR frames simultaneously. For the 6-bit implementation of Digit -Online decoder in single-frame mode, the minimum throughput achieved is 543Mbps at low SNRs. For the case of 13-bit Digit online decoder in frame interlaced mode, the minimum throughput achieved is 1028 Mbps. We present detailed analysis such as effect of SNR, decoder iterations, offset on decoder power. Apart from that, we also study effect of changing LLR precision on max clock frequency, logic utilization and comparison between bit-parallel and digit-online decoder.