Candidate: Mohammed Sajjad Jafri
Date: March 15, 2024
Time: 12:00pm to 1:00pm
Location: online (Webex); contact the candidate for information
Supervisor: Rodolfo Pellizzoni
Abstract:
In this thesis, we introduce a centralized performance monitoring infrastructure. In the current computing landscape, performance monitoring architectures are becoming more and more important for academic and industrial research. Considering the complexity of modern compute platforms, performance counters reveal valuable insight into the functioning of the platform, that can be exploited for debugging applications, improving performance, identifying bottlenecks, etc. In our proposed architecture, we envision a configurable Advanced Performance Monitoring Unit (APMU) connected to a set of small monitoring Event Units (EVU) installed in various hardware IPs that are distributed across the platform. These EVUs sent IP-related hardware events that can be collected in the APMU. The APMU has smart counters that are capable of operating on the incoming events, and a processor that can implement complex software mechanisms on the counter data. Our design allows for a efficient collection and correlation of event data, allowing the APMU to get a more holistic insight into the system behaviour, revealing low-level and often hard-to-know platform specific information. We also provide the specification for the APMU and standardize its interface with the generalized EVUs. We implement the design targeting a RISC-V compliant system with AXI4-based interconnections, along with a software stack to support programming on the APMU processor. The implemented design is emulated on an AMD Virtex UltraScale+ FPGA VCU118 device. To evaluate the implementation of our design, we present the hardware synthesis results for the FPGA, along with the performance results for a latency-based regulation case study.
All are welcome!