Low-Leakage ESD Power Supply Clamps in General Purpose 65 nm CMOS Technology
Manoj Sachdev and Ajoy Opal
Electrostatic discharge (ESD) is a well-known contributor to poor integrated circuit (IC) reliability and yield. As ICs become more complex, they are increasingly susceptible to such failures due to scaling of physical dimensions of devices and interconnect on a chip . These failures are caused by excessive electric field and/or excessive current densities and result in dielectric breakdown, electro-migration of metal lines and contacts. ESD can affect the ICs in its different life stages, from wafer-fabrication process to failure in the field. Furthermore, ESD events can damage the integrated circuit permanently (hard failure), or cause a latent damage (soft failure) .
ESD protection circuits consisting of I/O protection and ESD power supply clamps are routinely used in ICs to protect them against ESD damage. The main objective of the ESD protection circuit is to provide a low-resistive discharge path between any two pins in the chip in order to harmlessly discharge ESD energy without damaging the sensitive circuits. The main target of this thesis is to design ESD power supply clamps that have the lowest possible leakage current without degrading the ESD protection ability in general purpose TSMC 65 nm CMOS technology. ESD clamps should have very low-leakage current, and should be stable and immune against the power supply noise under the normal operating condition of the circuit core. In addition, the ESD clamps must be able to handle high currents under an ESD event.
In this thesis, four ESD power supply clamps are proposed and fabricated in GP TSMC 65 nm CMOS technology. The proposed ESD power supply clamps are: PMOS ESD power supply clamp with thyristor delay element (PTC), diode triggered power supply (DTC), PMOS ESD power supply clamp with thyristor delay element and diodes (PTDC), and NMOS ESD power supply clamp with level shifter delay element and diode (NLDC). Both DTC and PTC were able to provide a protection to the circuit core against ±125 V CDM stress by limiting the voltage between the two power rails to less than the oxide breakdown voltage of the core transistors, BVOXESD = 5 V. On the other hand, the PTDC and NLDC were designed to provide higher protection level, protection against ±300 V CDM stress.
Simulation results show that the proposed clamps are able to protect the circuit core against ±1.5 kV HBM and at least against ±125 V CDM stresses. The measurement results showed that all of the proposed clamps are immune against false triggering, and transient induced latch-up. Furthermore, all four designs have responded favorably to the 4 V ESD-like pulse voltage under both chip powered and not powered conditions and after the stress ends the designs turned off. Finally, TLP measurement results show that all four proposed designs meet the minimum design requirement of the ESD protection circuit in the 65 nm CMOS technology (i.e. HBM protection level of ±1.5 kV).
200 University Avenue West
Waterloo, ON N2L 3G1