Candidate: Ayman Jundi
Title: High Efficiency Broadband Power Amplifiers for Base Station Applications
Date: February 5, 2019
Time: 12:30 PM
Place: EIT 3142
Supervisor(s): Boumaiza, Slim
Abstract:
Current advances in wireless communication are driven by an increased demand for more bandwidth due to the transition into data-centric communication to fuel infotainment applications. The most trivial solution to scale the network capacity is an increase in the radio frequency (RF) spectrum allocated to service providers. However, this alone is not sufficient due to the scarce nature of this resource. In order to further address the scalability issue, new communication standards are created to be more spectrally efficient by using advanced modulation schemes which typically have higher peak to average power ration (PAPR).
High PAPR signals require power amplifier (PA) with increased back-off drain efficiency (DE) compared to classical PAs. Back-off efficiency enhancement techniques introduce new bottlenecks on the operating bandwidth and as a result it is quite challenging to service all bands with a single RF front-end. Multiple RF front-ends are hence used which increases cost, area and complexity. Moreover, this problem is compounded further with high output power PAs as, generally speaking, high output power requires low output impedance, and broadband matching networks are harder to design the further the impedance is from the standard 50. This problem is more relevant for base station (BS) PAs which require very high output power. In this thesis a new topology will be introduced which alleviates the bandwidth problem for high power PAs when being designed with high back-off efficiency.
After exploring the literature to understand the limitations of current implementations, it was found that the push-pull topology dominates the low frequency broadband high power PAs. In the absence of a complimentary transistor pairs the push-pull implantation requires the use of balanced to unbalanced (balun) transformers. Various balun implantations were hence investigated to identify the most suitable option for broadband planar implementation. As a result, a methodology was proposed to co-design the balun and the matching network in order to have better control over the harmonic impedance. An 85 W push-pull PA was then designed based on the proposed methodology with a multi-octave bandwidth as a demonstration of the wide-band potential of push-pull PAs at RF frequencies. The proposed methodology is targeted for mobile communication using off-the-shelf packaged devices.
Next, the two most popular techniques for back-off efficiency enhancement, i.e. envelope tracking (ET) and load modulation, were studied and the principle of load modulation was found to be more suitable for mobile BS. The most common implementation of load modulation is known as Doherty and it comes in two basic variations as introduced in the original publication. These two variations being the Parallel-Connected Load (PCL) and Series-Connected Load (SCL) Doherty Power Amplifier (DPA)s. The original design concepts are not only band limited but also ill-suited for high frequency designs where the transistors' parasitics introduce significant effect; however, later literature expanded on the original concept of the PCL variation which provided the needed flexibility for wider bandwidth implementations. Based on this and the proposed design methodology we used two push-pull amplifiers in a PCL DPA topology and demonstrated that the push-pull utilization doesn't have a significant impact on the bandwidth of the output combiner as an octave bandwidth was achieved with the use of digital Doherty.
Lastly, the thesis proposes a new approach for designing high power DPAs with extended bandwidth. It starts with a generic SCL DPA architecture to derive the equations that relate its underlying combiner's ABCD parameters to the transistor's optimum impedance and load impedance. These equations featured the possibility of significantly increasing the load impedance in SCL DPA compared to the one of the popular PCL DPA architecture. This is particularly beneficial when targeting very high power DPAs for macro-cell base stations and broadcast applications where very low load impedance can seriously complicate the design and limit the achievable bandwidth. To further maximize the load impedance increase, the proposed SCL DPA uses a push-pull topology for the main and peaking amplifier stages. A low-loss planar balanced to unbalanced transformer (balun) based combiner network is then utilized to realize the SCL DPA combiner while absorbing the transistors parasitics. The proposed approach was finally applied to design a proof-of-concept 350 W SCL DPA which operates over the band spanning from 720 to 980 MHz. The prototype demonstrated a peak output power of about 55 dBm with a 30% fractional bandwidth with a 6 dB back-off efficiency, measured using pulsed signal, between 46.6 % and 54.6 %. Furthermore, the modulated signal based measurement results confirmed the linearizability of the SCL DPA prototype while maintaining a back-off efficiency over 50% for a 7.1 dB peak to average power ratio signal.