Thursday, January 23, 2020 — 2:30 PM EST

Candidate: Kaship Sheikh

Title: Appropriateness of Imperfect CNFET Based Circuits for Error Resilient Computing Systems

Date: January 23, 2020

Time: 2:30 PM

Place: EIT 3142

Supervisor(s): Wei, Lan

 

Abstract:

With superior device performance consistently reported in extremely scaled dimensions, low dimensional materials (LDMs) including Carbon Nanotube Field Effect Transistor (CNFET) based technology have shown the potential to outperform silicon for future transistors in advanced technology nodes. Studies have also shown orders of magnitude improvement in energy efficiency possible with LDMs, in comparison to silicon at competing technology node. However, the current fabrication processes for these materials suffer from process imperfections and still seems to be inadequate to compete with silicon for the mainstream high volume manufacturing. Among the LDMs, CNFETs are the most widely studied and closest to high volume manufacturing. Recent works have shown significant increase in complexity of CNFET based systems with even demonstration of 16-bit microprocessor. However, design of such systems has involved significantly wider transistors, avoidance of certain logic combinations, and resulting complexity of several thousand transistors still far from the requirements of high performance general purpose computing systems having billions of transistors. For earlier technology adoption, CNFET seems to be suited for error resilient computing systems where errors during computation can be tolerated to certain degree. Such systems relax the need for precise circuits, perfect process while leverage the potential energy benefits of CNFET technology in comparison to conventional Si technology. In this thesis, we explore the potential application using less perfect CNFET process for error-resilient computing systems, including the impact of the process imperfections at the system level and methods to improve it.

 

The current most widely adopted fabrication process for CNFETs (separation and placement of solution based CNTs) also suffers from process imperfections, mainly from open CNTs due to missing of CNTs (in trenches connecting source and drain of CNFET). A fair evaluation of performance of CNFET based circuits should thus take into consideration the effect of open CNTs, resulting in reduced drive currents. At the circuit level, this leads to failures in meeting 1) minimum frequency requirement (due to increase in critical path delay), 2) noise suppression requirement. We present a methodology to accurately capture the effect of open CNT imperfection in the state of art CNFET model, for circuit-level performance evaluation (both delay and glitch vulnerability) of CNFET based circuits using SPICE. A Monte Carlo simulation framework is also provided to include the statistical effect of open CNT imperfection on circuit-level performance. We introduce important metrics to evaluate glitch vulnerability and also provide an effective link between glitch vulnerability and circuit topology.

 

Past few years have observed significant growth of interest in approximate computing for wide range of applications including signal processing, data mining, machine learning, image, video processing, etc where the result quality is not compromised appreciably by presence of few errors during computation. The ability to tolerate few errors during computation, thus relax the need to have precise circuits. Thus, the approximate circuits can be designed with lesser nodes, reduced stages and reduced capacitance at few nodes, consequently resulting in circuits with reduced critical path delays, enhanced noise suppression. We present a systematic methodology utilizing Reduced Ordered Binary Decision Diagrams (ROBDD) for generating approximate circuits, by taking example of 16-bit parallel prefix CNFET adders. The approximate adder generated has ~ 5 x reduction in average number of nodes failing glitch criteria (along paths to primary output) and 43.4% lesser Energy Delay Product (EDP) even at high open CNT imperfection, in comparison to ideal case of no open CNT imperfection, at a mean relative error of 3.3%.

 

Recent boom of deep learning has been made possible by VLSI technology advancement resulting in hardware systems, which can support deep learning algorithms. These hardware systems intend to satisfy the high-energy efficiency requirement of such algorithms, by adopting neuromorphic-computing architectures with significantly less energy compared to traditional Von Neumann architectures for hardware implementation of such algorithms. Deep Neural Networks (DNNs) belonging to deep learning domain and its use in wide range of applications such as image classification, speech recognition etc. Recent hardware systems have demonstrated implementation of complex neural networks at significantly less power. However, the complexity of applications and depths of DNNs are expected to drastically increase in future, imposing demanding requirement in terms of scalability and energy efficiency of hardware technology. CNFET technology can be an excellent alternative to meet the aggressive energy efficiency requirement for future DNNs. However, degradation in circuit-level performance due to open CNT imperfection can result in timing failure, thus distorting the shape of non-linear activation function, leading to significant degradation in classification accuracy. We present framework to obtain sigmoid activation function considering the effect of open CNT imperfection. A digital neuron is explored to generate the sigmoid activation function, which deviates from ideal case under imperfect process and reduced time period (increased clock frequency). The inherent error resilience of DNNs can however be utilized to mitigate the impact of imperfect process and maintain the shape of activation function. We utilize pruning of synaptic weight which combined with proposed approximate neuron significantly reduces the chance of timing failure, and help to maintain the activation function shape even at high process imperfection and higher clock frequency. We also provide framework to obtain classification accuracy of Deep Belief Network (class of DNNs based on unsupervised learning) using the activation functions obtained from SPICE simulations. By using both approximate neuron and pruning of synaptic weights, we achieve excellent system accuracy (only < 0.5% accuracy drop) with 25% improvement in speed, significant EDP advantage (56.7% less) even at high process imperfection, in comparison to base configuration of precise neuron and no pruning with ideal process, at no area penalty.

 

In conclusion, this thesis provides directions for potential applicability of CNFET based technology for error resilient computing systems. For this purpose, we present methodologies, which provide assessment of circuit-level performance of CNFET based circuits, considering process imperfections. We accomplish DBN framework for digit recognition, considering activation functions from SPICE simulations incorporating process imperfections. We demonstrate effectiveness of approximate neuron and synaptic weight pruning to mitigate the impact of high process imperfection on system accuracy.

Location 
EIT
Room 3142
200 University Avenue West

Waterloo, ON N2L 3G1
Canada

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