MASc seminar - Mustafa Osam FarajExport this event to calendar

Tuesday, August 16, 2016 — 9:30 AM EDT

Candidate

Mustafa Osam Faraj

Title

Side Channel Attack on Low Power FPGA Platform

Supervisor

Catherine Gebotys

Abstract

In today's advanced electronic age, people have become accustomed to using electronic devices to store and process their information. There is a general belief that the information is safe, due to the use of mathematically proven cryptographic systems in critical devices. However, in recent years, various side channel attacks have been used to break the security of systems that were thought to be completely safe. Side channel attacks are based on information gained through the physical implementation of a cryptosystem, rather than its mathematical construction. In this thesis work, an investigation is carried out to examine the susceptibility of the Hash-based Message Authentication Code standard based on the Secure Hash Algorithm (HMAC-SHA256) cryptosystem to a known correlation power analysis attack. For the purpose of this investigation, the cryptosystem was implemented on a low power Xilinx Field-Programmable Gate Array (FPGA) on the Side Channel Attack Standard Evaluation Board (SASEBO) platform. A secondary objective of the research work was to explore whether the SASEBO platform used may be easily modified to run side channel attacks on different cryptosystems. Four different side channel attacks were carried out on the HMAC-SHA256 implementation on the Xilinx Virtex-5 FPGA; two were based on power consumption measurements and two on electromagnetic (EM) emanation above the FPGA chip. This thesis has shown that SAESBO platform can be used as a testbed for examining the power side channel analysis of different cryptosystems with a small percentage of FPGA overhead. Although the EM emanations from SAESBO are not viable for side channel analysis, power from the on-chip core can be utilized. In addition the previously researched carry-propagate and pre-averaging techniques have been verified and found to be useful on this low power FPGA chip, requiring approximately 43776 traces for the guess of the correct secret intermediate values to reach among the top 5 ranked guesses.

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