MASc seminar - Rachna SrivastavaExport this event to calendar

Monday, August 24, 2015 — 3:00 PM EDT

Candidate

Rachna Srivastava

Title

Low-Noise Amplifier for Neural Recording

Supervisor

Vincent Gaudet

Abstract

With a combination of engineering approaches and neurophysiological knowledge of the central nervous system, a new generation of medical devices is being developed to link groups of neurons with microelectronic systems. By doing this, researchers are acquiring fundamental knowledge of the mechanisms of disease and innovating treatments for disabilities in patients who have a failure of communication along neural pathways.

A low-noise and low-power analog front-end circuit is one of the primary requirements for neural recording. The main function for the amplifier is to provide gain over the bandwidth of neural signals and to reject undesired frequency components. The chip developed in this thesis is a field-programmable analog front-end amplifier consisting of 16 programmable channels with tunable frequency response . A capacitively coupled two-stage amplifier is used. The first-stage amplifier is a low-noise amplifier, as it directly interfaces with the neural recording micro-electrodes; the second stage is a high-gain and high swing amplifier. A MOS resistor in the feedback path is used to get tunable low-cut-off frequency and reject the dc offset voltage.

Our design builds upon previous recording chips designed by two former graduate students in our lab. In our design, the circuits are optimized for low noise. Our simulations show the recording channel has a gain of 77.6 dB and input-referred noise of 6.9 µVrms over 15 Hz to 7.5 KHz. The chip is currently being fabricated in AMS 0.35 µm CMOS technology for a total die area of 3 mm×3 mm and consumes 2.9 mW.

Location 
EIT building
Room 3142

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