PhD defence - Hany Kashif

Thursday, September 17, 2015 9:00 am - 9:00 am EDT (GMT -04:00)


Hany Kashif


Deployment and Debugging of Real-Time Applications on Multicore Architectures


Sebastian Fischmeister and Hiren Patel


Of all computers, 98% are embedded systems and plenty of those are real-time control systems (DARPA, 2000). Testing and validation is an integral component of the software design process that ensures that the software under test is correct. However, providing such correctness guarantees is both difficult and expensive. A primary reason for this is the increasing size and complexity of modern software systems. In general, corrective costs of software are more than two folds the development costs (NASA, Bohem).

The process of diagnosis typically employs program tracing techniques. Program tracing techniques extract information from the program during execution, and form a trace of execution of the program. This is done by instrumenting (adding code to) the program to trace and/or monitor the program state. Logged information can be stored in dedicated logging memories or can be buffered and streamed off-chip to an external monitor. The designer inspects the trace after execution to identify potentially erroneous state information. In addition, the trace can provide the state information that serves as input to generate the erroneous output for reproducibility. These techniques are used during the software design process to test and validate the system, but they are also often used during deployment as well. This is to continue collecting trace information in the event of certain failures that require diagnosis.

For the sub-class of software systems known as real-time systems, the above-mentioned issues are further aggravated. This is because real-time systems demand guarantees on temporal behaviors in addition to functional correctness. Consequently, any instrumentation to the original program code for the purpose of program tracing may affect the temporal behaviors of the program. This perturbation of temporal behaviors raises issues during testing and validation in the software design process, and during deployment. In the former, violating the temporal constraints of the program may bias the execution of the program to certain operations. In the latter, deployment is simply not possible if the program may potentially miss its deadline. As a result, there is considerable interest in devising techniques to allow for program tracing without missing a programs deadline that is known as time-aware instrumentation. Hence, this thesis investigates time-aware instrumentation mechanisms to instrument programs without affecting their specified timing constraints and functional behavior.

Another challenge that arises from the increasing complexity of real-time applications, is the need for higher computational power. Due to the limits on power consumption and heat dissipation in processors, increasing their performance is not a viable solution anymore. Multi-core architectures pose themselves as a solution to the performance bottleneck. Providing timing guarantees for hard real-time systems, however, on multi-core interconnects is difficult. This is because conventional communication interconnects are designed to optimize the average-case performance. These, however, are a hindrance to accurately predicting the worst-case in interconnects. Therefore, researchers propose interconnects such as the priority-aware networks to satisfy the requirements of hard real-time systems. The priority-aware interconnects, however, lack the proper analysis techniques to facilitate the deployment of real-time systems. This thesis also investigates these analysis techniques including latency and buffer space analysis in the priority-aware interconnects, as well as algorithms for the proper deployment of the real-time applications to the multi-core platform.

The analysis techniques proposed in this thesis provide guarantees on the schedulability of real-time systems on multi-core architectures. These guarantees are based on reducing contention in the interconnect while simultaneously accurately computing the worst-case communication latencies. While these worst-case latencies provide bounds for computing the overall worst-case execution time of applications on a multi-core platform, they also provide means to assigning debugging budgets required by the time-aware instrumentation mechanisms. The results in this thesis show promise for using priority-aware interconnects as an underlying communication interconnect in multi-core platforms.