Candidate: Hai Huang
Title: Novel Predistortion System for Small-Cell Base Stations and Wideband Transmitters
Date: November 27, 2020
Time: 9:00 AM
Place: REMOTE ATTENDANCE
Supervisor(s): Levine, Peter - Boumaiza, Slim
To meet the growing demand of mobile data, wireless networks introduces various technologies to increase the system capacity. On one hand, small-cell base station are adopted in large number to serve the reduced cell size; on the other hand, millimetre wave (mm-wave) system with large antenna arrays are expected to transmitted ultra-wideband signals in fifth generation (5G) networks. Power amplifier (PA), responsible for boosting the radio frequency (RF) signal power, is the most critical component in a base station transmitter, and dominates the efficiency and linearity of the system. The design challenge of the PA to achieve the contradictory requirements of good efficiency and linearity are usually addressed by linearization techniques, particularly the digital predistortion (DPD) system. However, existing DPD solution faces increasing difficulties to keep up with the new development in base stations.
Analog and radio frequency predistortion techniques has received renewed attention due to their low power nature, which is desired in sub-6 GHz small-cell base station transmitters. But their linearization capability is limited largely by difficulties in implementing the needed predistortion models in analog circuits due to hardware complexity. On the other hand, despite significant development in DPD models, the implementation of the engine in hardware received little attention. Yet conventional implementation of DPD engine is limited by the maximum clock frequency of the digital circuits and cannot be scaled to satisfy the growing bandwidth of the transmitted signals. Common to both analog and digital solutions, the transmitter-observation-receiver (TOR) needed to capture the PA outputs also requires analog-to-digital converters (ADCs) whose complexity and power consumption increases with signal bandwidth, and new innovation in feedback and training is required for both situations. This thesis presents a number of contributions to address the above challenges.
To reduce the power overhead of linearization system, an analog-RF predistortion (ARFPD) system using a novel predistortion model is introduced. The proposed finite-impulse-response assisted envelope memory polynomial (FIR-EMP) allowed for reduction of hardware implementation complexity while maintaining good linearization capacity and low power overhead. A two-step small-signal-assisted parameter identification (SSAPI) algorithm is devised to estimate the parameters of the two main blocks of the FIR-EMP model, so the training can be completed efficiently. An ARFPD test bench, which incorporates major RF components, has been built to assess the validity of the proposed FIR-EMP scheme and the SSAPI algorithm. Measurement results have shown that the proposed FIR-EMP model using the SSAPI algorithm can successfully linearize multiple PAs driven with various wideband and carrier-aggregated signals of up to 80~MHz modulation bandwidth for sub-6 GHz 5G systems.
Next, a hardware-efficient real-time DPD system with scalable linearization bandwidth for ultra-wideband 5G mm-wave transmitters is proposed. It uses a novel parallel-processing DPD engine architecture to process multiple samples per clock cycle, overcoming the limits on linearization bandwidth imposed by the maximum clock rate of the digital circuits using conventional DPD implementation. Potentially unlimited linearization bandwidth can be achieved by current digital circuit technologies using the proposed system. The linearization performance and bandwidth scalability of the proposed system were demonstrated experimentally using a silicon-based Doherty PA (DPA) with 400 MHz wideband signal operating at 28 GHz, and over-the-air measurements using a 64-element beamforming array with 800 MHz wideband signal, also at 28 GHz. The proposed DPD system achieved over 2.4 GHz linearization bandwidth using only a 300 MHz core clock for the digital circuits.
Finally, to reduce the power consumption and cost of the TOR, a new approach to train the predistortion using a subsampled feedback signal is presented. Using aliased samples of the PA output captured at either of the baseband or IF, the proposed algorithm is able to compute the coefficients of the predistortion engine to linearize the PA using a direct learning architecture. Both the baseband scheme and the IF scheme can achieve linearization performance comparable to full-rate system experimentally. Implemented together with a parallel processing based DPD engine on field-programmable gate array (FPGA) based system-on-chip (SOC), the proposed feedback and training solution achieves over 2.4 GHz linearization bandwidth using an ADC operating at a clock rate of 200 MHz. Its performance is demonstrated experimentally by linearizing a silicon DPA with 200 MHz and 400 MHz signals in conductive measurements, and a 64-element beamforming array with 400 MHz and 800 MHz signals in over-the-air (OTA) testing.