PhD Seminar: Balancing Timing Predictability and High-Performance in Cache Coherence Mechanisms

Tuesday, March 2, 2021 10:00 am - 10:00 am EST (GMT -05:00)

Candidate: Anirudh Mohan Kaushik

Title: Balancing Timing Predictability and High-Performance in Cache Coherence Mechanisms

Date: March 2, 2021

Time: 10:00 AM


Supervisor(s): Patel, Hiren


Predictable hardware cache coherence is an attractive data communication mechanism between safety-critical tasks deployed on real-time multi-core platforms due to its timing predictability and high-performance benefits. However, from a worst-case analysis standpoint, alternative data communication mechanisms appear in favorable light for adoption in real-time multi-core platforms. This is because alternative data communication mechanisms such as cache bypassing offer lower worst-case latency (WCL) bounds for memory requests compared to predictable hardware cache coherence mechanisms irrespective of the performance benefits of the latter over the former.

In this talk, I will describe a systematic approach towards designing predictable cache coherence mechanisms that offer low WCL and high-performance. I will describe a formal framework that concisely captures the key reasons behind the high WCL in existing predictable cache coherence mechanisms. Guided by this formal framework, I will describe one technique that employs protocol changes to achieve low WCL and high-performance. Evaluation shows that the new cache coherence mechanisms resulting from the proposed technique have the same low WCL as alternative mechanisms, and still maintain a significant average-case performance advantage (up to 5x speedup) over the alternative mechanisms.