PhD Seminar: Hardware Implementation of a High-Speed Low-Power Decoder for Low Density Lattice CodesExport this event to calendar

Monday, July 16, 2018 — 2:00 PM EDT

Candidate: Rachna Srivastava

Title: Hardware Implementation of a High-Speed Low-Power Decoder for Low Density Lattice Codes

Date: July 16, 2018

Time: 2:00 pm

Place: EIT 3151-3153

Supervisor(s): Gaudet, Vincent - Mitran, Patrick

Abstract:

In this research work, we propose an approach for the hardware implementation of a decoder for low-density lattice codes. Though the available literature shows that low-density lattice codes can be useful for several applications, but very little work has been driven by hardware implementation. Our goal in this work is to develop a hardware implementation of a high-throughput low-power LDLC decoder. Several approximations are used to make the implementation feasible. To reduce the decoder complexity and storage requirement, we use the fact that Gaussian mixtures can be represented entirely by three parameter lists of means, variances and weights. So, in iterative decoding, triples of these parameters are passed as messages instead of complete Gaussian mixtures.

In order to reduce the complexity further, the Gaussian mixtures propagated in decoding iterations can be approximated to a fixed number of Gaussians. In the literature, the Gaussian mixtures are approximated to single and multiple Gaussians. In our implementation we also approximate the Gaussian mixtures to a reduced Gaussian mixture with fewer components to keep the hardware implementation simple.

Location 
EIT
Room 3151-3153
200 University Avenue West

Kitchener, ON N2L 3G1
Canada

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