Jaspal Singh Shah
Low Power Soft Error Robust Embedded SRAM
Soft errors are radiation induced ionization events (induced by energetic particles like alpha particles, cosmic neutron, etc.) that cause transient errors in integrated circuits. The circuit can always recover from such errors as the underlying semiconductor material is not damaged and hence, they are called soft errors. In nanometer technologies, the reduced node capacitance and supply voltage coupled with high packing density and lack of masking mechanisms are primarily responsible for increased susceptibility of SRAMs towards soft errors. Coupled with these are the process variations (effective length, width, and threshold voltage), which are prominent in scaled-down technologies. Typically, SRAM constitutes upto 90% of the die in microprocessors and SoCs(System-on-Chip). Hence, the soft errors in SRAMs pose a potential threat to the reliable operation of the system.
In this work, a soft error robust eight transistor SRAM cell (8T) are proposed to establish a balance between low power consumption and soft error robustness. Using metrics like access time, leakage power, and sensitivity to single event transient (SET), the proposed approach is evaluated. For the purpose of analysis and comparison the results of 8T cell are compared with a standard 6T SRAM cell and the state of the art soft error robust SRAM cells. Based off simulation results in a 65 nm commercial CMOS process, the 8T cell demonstrates higher immunity to SETs along with smaller area and comparable leakage power. A 32 kb array of 8T cells was fabricated in silicon. After functional verification of the test chip, a radiation test was conducted to evaluate the soft error robustness.
As SRAM cells are scaled aggressively to increase the overall packing density, the smaller transistors exhibit higher degrees of process variation and mismatch, leading to larger offset voltages. For SRAM sense amplifiers, higher offset voltages lead to an increased likelihood of an incorrect decision. To address this issue, a sense amplifier capable of canceling the input offset voltage is presented. The simulated and measured results in 180 nm technology show that the sense amplifier is capable of detecting a 4 mV differential input signal under dc and transient conditions. The proposed sense amplifier when compared with a conventional sense amplifier have a similar die area and a greatly reduced offset voltage. Additionally, a dual input sense amplifier architecture is proposed with corroborating silicon results to show that it requires smaller differential input to evaluate correctly.
Manoj Sachdev and David Nairn