PhD seminar - Pierce I-Jen ChuangExport this event to calendar

Thursday, September 25, 2014 — 1:00 PM EDT

Candidate

Pierce I-Jen Chuang

Title

High-Performance, Energy-Efficient CMOS Arithmetic Circuits

Supervisors

Manoj Sachdev and Vincent Gaudet

Abstract

In a modern microprocessor, data-path/arithmetic circuit has always been an important building block in delivering high-performance, energy-efficient computing, because arithmetic operations such as addition and binary number comparison are two of the most commonly used computing instructions. Besides the manufacturing CMOS process, the two most critical design considerations for arithmetic circuits are the logic style and micro-architecture. In this seminar, a constant-delay (CD) logic style is proposed targeting full-custom high-speed applications. The constant delay characteristic of this logic style (regardless of the logic type) makes it suitable to implement complicated logic expressions such as addition. CD logic exhibits a unique characteristic where the output is pre-evaluated before the inputs from the preceding stage are ready. This feature enables performance advantage over static and dynamic domino logic styles in a single cycle, multi-stage circuit block. Several design considerations including timing window width adjustment and clock distribution are discussed. To conrm CD logic's potential, a 148 ps, single-cycle 64-bit adder with CD logic implemented in the critical path is fabricated in a 65-nm, 1-V CMOS process. A new 64-bit Ling adder micro0architecture, which utilizes both inversion and absorption properties to minimize the number of CD logic and the number of logic stage in the critical path, is also proposed. At 1-V supply, this adder's measured worst-case power and leakage power are 135 mW and 0.22 mW, respectively. A single-cycle 64-bit binary comparator utilizing a radix-2 tree structure is also proposed. This comparator architecture is specically designed for static logic to achieve both low-power and high-performance operation, especially in low input data activity environments. At 65-nm technology with 25% (10%) data activity, the proposed design demonstrates 2.3 (3.5) and 3.7 (5.8) power and energy-delay product eciency, respectively. This comparator is also 2.7 faster at iso-energy (80 fJ) or 3.3 more energy ecient at iso-delay (200 ps) than existing designs.

Location 
EIT building
Room 3142

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