Implementing FPGA-optimized Systolic Arrays using 2D Knapsack and Evolutionary Algorithms
Candidate: Harry Chan Chan
Title: Implementing FPGA-optimized Systolic Arrays using 2D Knapsack and Evolutionary Algorithms
Date: November 26, 2021
Time: 18:00
Place: MS Teams
Supervisor(s): Kapre, Nachiket
Abstract:
Underutilization of FPGA resources is a significant challenge in the deployment of FPGAs as neural network accelerators.
We propose an FPGA-optimized systolic array architecture to improve the CNN inference throughput by orders of magnitude through