ECE 621 - Fall 2015

ECE 621 - Computer Organization

Course description

This is a graduate course on computer architecture focusing on quantitative methods for cost and performance design tradeoffs. This course covers the fundamentals of classical and modern general processor design. This includes organization, performance, instruction-sets, pipelining, caches, virtual memory, I/O, superscalar, out-of-order execution, speculative execution, multithreaded processors, multiprocessors, cache coherency, memory consistency and synchronization techniques; and special-purpose architectures.

Class days, times, building, and room number

Lectures: To be determined.
Midterm exam: To be determined.
Final exam: To be determined.

Instructor

Professor Hiren Patel
Office: E5 4018
e-mail: h.patel+ece621f2015@ecemail.uwaterloo.ca
Office hours: To be determined.

Note: When sending email to the course instructor:

1. Ensure that the email’s subject contains ECE621F15.
2. The email is sent from a University of Waterloo mail server (e.g. engmail, ecemail, mailservices, connect, etc.) with your official UWid. Email from gmail and the like will not be received.

Course website

The course website is on LEARN.
This website contains all lecture materials, problem sets/solutions, and it will be used as the primary medium for communication.

Course textbook

• D. A. Patterson and J. L. Hennessy, Computer Architecture: A Quantitative Approach, Fifth Edition, Morgan Kaufmann, 2011.

Course objectives

• Become fluent in the architectures of pipelined high performance processors
• Be competent in the instruction scheduling strategies in integer/floating point pipelines and reducing pipeline stalls due to various hazards
• Multiprocessor performance limitations, distributed cache coherence protocols and multiprocessor synchronization problems.

Course prerequisites

No formal course requirements are necessary; however, students should are expected to be familiar with the basics of instruction-set architectures, assembly language programming, pipelines and caches.

Evaluation

The course grade will be based on the following components:

Note:

1. The midterm and final exams will be held during the official examination schedule.
2. The midterm exam and final exam are closed books and closed notes. A simple calculator will be allowed, but no computers or PDAs.
3. A student missing any of the exams will automatically receive a score of 0 for that exam.
4. A student missing any of the exams must provide appropriate documentation (e.g. verification of illness form of an illness, a death certificate, etc.).
5. If a student misses the midterm exam, and provides the appropriate documentation, then the final exam will be worth 70% of the final course mark.
6. To receive a passing mark for the course, the student must receive a score of 50% or higher in the final exam.
7. The instructor reserves the right to curve any of the exam and project grades, and the final marks.
8. Any violations of academic honesty and integrity policies will result in an automatic failure of the course with a final score of 0.

Project Overview

Students can work in groups of maximum two people.

Cycle-accurate Implementation of a MIPS processor: The group will design and implement a cycle- accurate MIPS processor architecture. Further details on the specifics of the architecture and compiler suite used will be provided in class.

Demo: The group will demonstrate their implementation. Further details on the demonstration will be provided later, but expect there to be intermediate demonstration requirements.

Note:

1. The student must obtain 12.5% out of 25% on the project to pass this course.
2. The project will be split into 6 project deliverables (PD0 – PD5). The points associated with each PD are as follows: (PD0, PD1, PD2, PD3, PD4, PD5) = (1, 3, 3, 3, 3, 12) = 25% of final grade.
3. Late submission result in a 0 for that PD. No exceptions will be made.

Course Topics

This is a list of tentative topics to be covered this term.

Important Notes

• Academic integrity: In order to maintain a culture of academic integrity, members of the University of Waterloo community are expected to promote honesty, trust, fairness, respect and responsibility.
• Grievance: A student who believes that a decision affecting some aspect of his/her university life has been unfair or unreasonable may have grounds for initiating a grievance. Read Policy 70, Student Petitions and Grievances, Section 4. When in doubt please be certain to contact the department’s administrative assistant who will provide further assistance.
• Discipline: A student is expected to know what constitutes academic integrity to avoid committing an academic offence, and to take responsibility for his/her actions. A student who is unsure whether an action constitutes an offence, or who needs help in learning how to avoid offences (e.g., plagiarism, cheating) or about “rules” for group work/collaboration should seek guidance from the course instructor, academic advisor, or the undergraduate Associate Dean. For information on categories of offences and types of penalties, students should refer to Policy 71, Student Discipline. For typical penalties check Guidelines for the Assessment of Penalties.
• Appeals: A decision made or penalty imposed under Policy 70 (Student Petitions and Grievances) (other than a petition) or Policy 71 (Student Discipline) may be appealed if there is a ground. A student who believes he/she has a ground for an appeal should refer to Policy 72 (Student Appeals).
• Note for students with disabilities: The AccessAbility Services, located in Needles Hall, Room 1132, collaborates with all academic departments to arrange appropriate accommodations for students with disabilities without compromising the academic integrity of the curriculum. If you require academic accommodations to lessen the impact of your disability, please register with the AccessAbility Services at the beginning of each academic term.