Sai Charan Gurrappadi and Gleb Nikonov
Case revision date: 
4 Pages (Case Study)

Block diagram of Tegra 3 cluster architecture

A long-time frontrunner in the desktop graphics market, Nvidia Corporation, located in Santa Clara, California, has recently expanded their product line to feature mobile devices. The Tegra 3 system-on-a-chip (SoC) integrates Nvidia’s latest central processing, graphics processing, and memory controller hardware into a single chip. Unlike typical desktop processors, mobile processors are limited by a device’s battery and the energy it is capable of delivering. Providing the right balance between processing capability and battery life requires the optimization of hardware-kernel interaction, as well as the processor’s reaction to the demands of software.

Sai Charan Gurrappadi, a fourth-year Mechatronics Engineering student, was asked to analyze the central processor usage and its impact on power consumption and battery life. 

Learning objectives: 

The teaching objectives of this case study are to introduce the basics of power within an integrated circuit, the power management as specific to the Tegra 3 architecture, to provide an explanation for current power management policies and to necessitate the development of a suitable replacement/addition to current power policy in order to reduce power consumption. This case study can be used as effective material for Digital Hardware Systems (ECE 327).

Key words: 
Dynamic Power; Leakage Power; AutoHotplug Algorithm; Kernel function; Runnable threads algorithm
CEAB attributes: 
Problem Analysis; Creativity; A knowledge base for engineering
Module 01 - Case Study
Module 02 - Runnable Threads Algorithm Design (Restricted to educators only)
Module TN - Teaching Note (Restricted to educators only)

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