Waterloo Institute for Nanotechnology
Mike & Ophelia Lazaridis Quantum-Nano Centre, QNC 3606
University of Waterloo
200 University Avenue West,
Waterloo, ON N2L 3G1
519-888-4567, ext. 38654
win-office@uwaterloo.ca
Research interests: low dimensional materials based integrated systems for energy storage, conversion and delivery
Lan received her B. S. in Microelectronics and Economics from Peking University, Beijing, China in 2005 and M. S. and Ph. D. in Electrical Engineering from Stanford University, Stanford, USA (with Prof. H. –S. Philip Wong) in 2007 and 2010, respectively.
Before joining UWaterloo in 2014, Lan worked at Altera Corporation (now part of Intel Corporation) in San Jose, California, where her responsibilities included foundry technology evaluation, power management and Stratix X FPGA product development with Intel 14nm technology. Lan also worked as a post-doctoral associate in Microsystems Technology Laboratories, Massachusetts Institute of Technology under Prof. Dimitri Antoniadis.
Lan's research focuses on device-circuit interactive design and optimization, integrated nanoelectronic systems with imperfect technologies (e.g. low-dimensional materials based transistors and non-volatile memories with imperfect materials, process and reliability failures), GaN-based technology for milliemeter wave communication, and self-powered grid sensing and monitoring systems. For more information regarding her research activities, please see the webpage of Waterloo Emerging Integrated Systems Group (WEIS)
Lan has served on the Technical Program Committee of IEDM (2011-2012), ISLPED (2013), VSLI-TSA (2013- ), GLSVLSI (2017- ), S3S (2018- ) and was listed as one of the key contributors to the PIDS (Process Integration, Devices, and Structures) Chapter of ITRS (International Technology Roadmap for Semiconductors) 2009 Edition. She is the co-developer of the MIT Virtual Source GaN HEMT (MVSG) Compact Model, which is an Industry Standard approved and supported by the Compact Model Coalition for GaN HEMT compact model.
PhD, Electrical Engineering, Stanford University, USA, 2010
MS, Electrical Engineering, Stanford University, USA, 2007
BS, Microelectronics and Economics, Peking University, China, 2005
Device-circuit interactive design and optimization
Low-dimensional materials based integrated nanoelectronic systems
GaN-based technology
X. Chen*, S. Boumaiza, L. Wei, “Modeling Self-Heating in GaN HEMTs using Two Heat Sources,” submitted to IEEE Electron Device Letters (EDL), 2019.
X. Chen*, S. Boumaiza, L. Wei, “Self-Heating and Equivalent Channel Temperature in Short Gate Length GaN HEMTs,” accepted by IEEE Transactions on Electron Devices (TED). 2019.
Z. Yang*, S. Zarabi*, E. Fernandes*, I. Rua, H. Debeda, A. Salehian, D. Nairn, L. Wei, “A Simple Wireless Sensor Node System for Electricity Monitoring Applications: Design, Integration, and Testing with Different Piezoelectric Energy Harvesters,” Sensors. No. 11, 2018.
E. Fernandes*, M. Blake, I. Rue, S. Zarabi*, H. Debeda, D. Nairn, L. Wei, A. Salehian, “Design, Fabrication, and Testing of a Low Frequency MEMS Piezoelectromagnetic Energy Harvester,” p.1 – 16, Smart Materials and Structures (SMS), vol. 27, No. 3, 2018
A. Tosson*, S. Yu, M. Anis and L. Wei, “Proposing a Solution for Single-Event Upset in 1T1R RRAM Memory Arrays,” IEEE Transaction on Nuclear Science (TNS), vol. 65, No. 6, pp 1239-1247, Jun. 2018
A. Tosson*, S. Yu, M. Anis, and L. Wei, “A Study of the Effect of RRAM Reliability Soft Errors on the Performance of RRAM-based Neuromorphic Systems,” IEEE Transactions on Very Large Scale Integration (TVLSI), Vo. 25, No. 11, pp 3125-3137, Nov. 2017
H. Zhang*, M. Gupta, J. Watt and L. Wei, "Effective Drive Current for Pass-Gate Transistors," in IEEE Transactions on Electron Devices (TED), vol. 63, no. 8, pp. 2999-3004, Aug. 2016.
K. Sheikh*, S-J. Han, and Lan Wei, "CNFET With Process Imperfection: Impact on Circuit-Level Yield and Device Optimization," IEEE Transactions on Circuits and Systems I: Regular Papers, (TCAS-I) vol. 63, no. 12, pp. 2209-2221, 2016.
J. Luo, L. Wei, C.-S. Lee, A. D. Franklin, X. Guan, E. Pop, D. A. Antoniadis, H.-S. P. Wong, “A Compact Model for Carbon Nanotube Field-Effect Transistors Including Non-Idealities and Calibrated with Experimental Data Down to 9 nm Gate Length,” IEEE Transactions on Electron Devices, vol 60, No 6, p.1834, 2013.
L. Wei, O. Mysore, D. A. Antoniadis, "Virtual-Source-Based Self-Consistent Current and Charge FET Models: From Ballistic to Drift-Diffusion Velocity-Saturation Operation,"Electron Devices, IEEE Transactions on, vol.59, no.5, pp.1263-1271, May 2012.
Z. Zhang, A. Lin, N. Patil, H. Wei, L. Wei, H.-S. P. Wong, and S. Mitra, “Robust Digital VLSI using Carbon Nanotubes” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 31, No. 4, pp. 453-471, 2012.
L. Wei, D. Frank, L. Chang, and H.-S. P. Wong, “Non-iterative Compact Model for Intrinsic Carbon Nanotube FETs: Quantum Capacitances and Transport,” IEEE Transactions on Electron Devices, vol. 58, No. 8, pp. 2456-2465, August 2011.
L. Wei, S. Oh, H. –S. P. Wong, “Technology Assessment Methodology for Complementary Logic Applications based on Energy-Delay Optimization,” IEEE Transactions on Electron Devices, vol. 58, No. 8, pp. 2430-2439, August 2011.
L. Wei, F. Boeuf, T. Skotnicki, and H.-S. P. Wong, “Parasitic Capacitances: Analytical Models and Impact on Circuit-Level Performance,” IEEE Transactions on Electron Devices, vol. 58, No. 5, pp. 1361-1370, May 2011.
L. Wei, J. Deng, L.-W. Chang, K. Kim, C.-T. Chuang and H. -S. P. Wong, "Selective Device Structure Scaling and Parasitics Engineering: A Way to Extend the Technology Roadmap,"IEEE Transactions on Electron Devices, pp. 312-320, Feb 2009.
L. Wei, J. Deng, H.-S. P. Wong, “Modeling and Performance Comparison of 1-D and 2-D Devices Including Parasitic Gate Capacitance and Screening Effect,” IEEE Transactions on Nanotechnology, vol. 7, No. 6, pp. 720 – 727, November, 2008.
Stanford University, USA (Jan 2009) , Johns Hopkins University, USA (Feb 2009), University of Southern California, USA (Mar 2009), University of California San Diego, USA (Mar 2009), University of California Riverside, USA (Mar 2009), Carnegie Mellon University, USA (Mar 2009), Shanghai Jiaotong University, China (Apr 2009), University of California Berkeley, USA (Apr 2009)
Pennsylvania State University, USA (Nov 2011), Semiconductor Manufacturing International Corporation, China, (Jan 2012), Chinese University of Hong Kong, Hong Kong (Jan 2012), Altera Corporation, USA (Feb 2012), Cornell University, USA (Mar 2012), University of Toronto, Canada (Apr 2012), IBM Semiconductor Research and Development Center, USA (May 2012), Qualcomm Research Center, USA (May 2012), University of Waterloo, Canada (Jul 2012), University of Houston, USA (Aug 2012).
Waterloo Institute for Nanotechnology
Mike & Ophelia Lazaridis Quantum-Nano Centre, QNC 3606
University of Waterloo
200 University Avenue West,
Waterloo, ON N2L 3G1
519-888-4567, ext. 38654
win-office@uwaterloo.ca
The University of Waterloo acknowledges that much of our work takes place on the traditional territory of the Neutral, Anishinaabeg and Haudenosaunee peoples. Our main campus is situated on the Haldimand Tract, the land granted to the Six Nations that includes six miles on each side of the Grand River. Our active work toward reconciliation takes place across our campuses through research, learning, teaching, and community building, and is co-ordinated within the Office of Indigenous Relations.