Lan Wei

Professor, Electrical and Computer Engineering

Research interests: low dimensional materials based integrated systems for energy storage, conversion and delivery

Biography

Lan received her B. S. in Microelectronics and Economics from Peking University, Beijing, China in 2005 and M. S. and Ph. D. in Electrical Engineering from Stanford University, Stanford, USA (with Prof. H. –S. Philip Wong) in 2007 and 2010, respectively.

Before joining UWaterloo in 2014, Lan worked at Altera Corporation (now part of Intel Corporation) in San Jose, California, where her responsibilities included foundry technology evaluation, power management and Stratix X FPGA product development with Intel 14nm technology. Lan also worked as a post-doctoral associate in Microsystems Technology Laboratories, Massachusetts Institute of Technology under Prof. Dimitri Antoniadis.

Lan's research focuses on device-circuit interactive design and optimization, integrated nanoelectronic systems with imperfect technologies (e.g. low-dimensional materials based transistors and non-volatile memories with imperfect materials, process and reliability failures), GaN-based technology for milliemeter wave communication, and self-powered grid sensing and monitoring systems. For more information regarding her research activities, please see the webpage of Waterloo Emerging Integrated Systems Group (WEIS)

Lan has served on the Technical Program Committee of IEDM (2011-2012), ISLPED (2013), VSLI-TSA (2013- ), GLSVLSI (2017- ), S3S (2018- ) and was listed as one of the key contributors to the PIDS (Process Integration, Devices, and Structures) Chapter of ITRS (International Technology Roadmap for Semiconductors) 2009 Edition. She is the co-developer of the MIT Virtual Source GaN HEMT (MVSG) Compact Model, which is an Industry Standard approved and supported by the Compact Model Coalition for GaN HEMT compact model.

Education

  • PhD, Electrical Engineering, Stanford University, USA, 2010

  • MS, Electrical Engineering, Stanford University, USA, 2007

  • BS, Microelectronics and Economics, Peking University, China, 2005

Lan Wei

Research

Research Interests

  • Device-circuit interactive design and optimization

  • Low-dimensional materials based integrated nanoelectronic systems

  • GaN-based technology

Publications

Refereed Journal Publications

  • X. Chen*, S. Boumaiza, L. Wei, “Modeling Self-Heating in GaN HEMTs using Two Heat Sources,” submitted to IEEE Electron Device Letters (EDL), 2019.

  • X. Chen*, S. Boumaiza, L. Wei, “Self-Heating and Equivalent Channel Temperature in Short Gate Length GaN HEMTs,” accepted by IEEE Transactions on Electron Devices (TED). 2019.

  • Z. Yang*, S. Zarabi*, E. Fernandes*, I. Rua, H. Debeda, A. Salehian, D. Nairn, L. Wei, “A Simple Wireless Sensor Node System for Electricity Monitoring Applications: Design, Integration, and Testing with Different Piezoelectric Energy Harvesters,” Sensors. No. 11, 2018.

  • E. Fernandes*, M. Blake, I. Rue, S. Zarabi*, H. Debeda, D. Nairn, L. Wei, A. Salehian, “Design, Fabrication, and Testing of a Low Frequency MEMS Piezoelectromagnetic Energy Harvester,” p.1 – 16, Smart Materials and Structures (SMS), vol. 27, No. 3, 2018

  • A. Tosson*, S. Yu, M. Anis and L. Wei, “Proposing a Solution for Single-Event Upset in 1T1R RRAM Memory Arrays,” IEEE Transaction on Nuclear Science (TNS), vol. 65, No. 6, pp 1239-1247, Jun. 2018

  • A. Tosson*, S. Yu, M. Anis, and L. Wei, “A Study of the Effect of RRAM Reliability Soft Errors on the Performance of RRAM-based Neuromorphic Systems,” IEEE Transactions on Very Large Scale Integration (TVLSI), Vo. 25, No. 11, pp 3125-3137, Nov. 2017

  • H. Zhang*, M. Gupta, J. Watt and L. Wei, "Effective Drive Current for Pass-Gate Transistors," in IEEE Transactions on Electron Devices (TED), vol. 63, no. 8, pp. 2999-3004, Aug. 2016.

  • K. Sheikh*, S-J. Han, and Lan Wei, "CNFET With Process Imperfection: Impact on Circuit-Level Yield and Device Optimization," IEEE Transactions on Circuits and Systems I: Regular Papers, (TCAS-I) vol. 63, no. 12, pp. 2209-2221, 2016.

  • J. Luo, L. Wei, C.-S. Lee, A. D. Franklin, X. Guan, E. Pop, D. A. Antoniadis, H.-S. P. Wong, “A Compact Model for Carbon Nanotube Field-Effect Transistors Including Non-Idealities and Calibrated with Experimental Data Down to 9 nm Gate Length,” IEEE Transactions on Electron Devices, vol 60, No 6, p.1834, 2013.

  • L. Wei, O. Mysore, D. A. Antoniadis, "Virtual-Source-Based Self-Consistent Current and Charge FET Models: From Ballistic to Drift-Diffusion Velocity-Saturation Operation,"Electron Devices, IEEE Transactions on, vol.59, no.5, pp.1263-1271, May 2012.

  • Z. Zhang, A. Lin, N. Patil, H. Wei, L. Wei, H.-S. P. Wong, and S. Mitra, “Robust Digital VLSI using Carbon Nanotubes” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 31, No. 4, pp. 453-471, 2012.

  • L. Wei, D. Frank, L. Chang, and H.-S. P. Wong, “Non-iterative Compact Model for Intrinsic Carbon Nanotube FETs: Quantum Capacitances and Transport,” IEEE Transactions on Electron Devices, vol. 58, No. 8, pp. 2456-2465, August 2011.

  • L. Wei, S. Oh, H. –S. P. Wong, “Technology Assessment Methodology for Complementary Logic Applications based on Energy-Delay Optimization,” IEEE Transactions on Electron Devices, vol. 58, No. 8, pp. 2430-2439, August 2011.

  • L. Wei, F. Boeuf, T. Skotnicki, and H.-S. P. Wong, “Parasitic Capacitances: Analytical Models and Impact on Circuit-Level Performance,” IEEE Transactions on Electron Devices, vol. 58, No. 5, pp. 1361-1370, May 2011.

  • L. Wei, J. Deng, L.-W. Chang, K. Kim, C.-T. Chuang and H. -S. P. Wong, "Selective Device Structure Scaling and Parasitics Engineering: A Way to Extend the Technology Roadmap,"IEEE Transactions on Electron Devices, pp. 312-320, Feb 2009.

  • L. Wei, J. Deng, H.-S. P. Wong, “Modeling and Performance Comparison of 1-D and 2-D Devices Including Parasitic Gate Capacitance and Screening Effect,” IEEE Transactions on Nanotechnology, vol. 7, No. 6, pp. 720 – 727, November, 2008.

Refereed Conference Papers

  • L. Yu, O. Mysore, L. Wei, L. Daniel, D. Antoniadis, I. Elfade, D. Boning, “An Ultra-Compact Virtual Source FET Model for Deeply-Scaled Devices: Parameter Extraction and Validation for Standard Cell Libraries and Digital Circuits,” 18th Asia and South Pacific Design Automation Conference (ASPDAC 2013), pp. 521-526, 2013.
  • L. Yu, L. Wei, D. Antoniadis, I. Elfadel, D. Boning, “Statistical Modeling with the Virtual Source MOSFET Model,” 2013 The Design, Automation, and Test in Europe Conference (DATE 2013), pp. 1454-1457, 2013.
  • U. Radhakrishna, L. Wei, D.-S. Lee, T. Palacios, D. A. Antoniadis, “Physics-based GaN HEMT Transport and Charge Model: Experimental Verification and Performance Projection,” 2012 IEEE International Electron Devices Meeting (IEDM 2012), paper 13.6, Dec, 2012.
  • C. Sun, C.-H. Chen, G. Kurian, L. Wei, J. Miller, A. Agarwal, L.-S. Peh and V. Stojanovic , “DSENT – A Tool Connecting Emerging Photonics with Electronics for Opto-Electronic Networks-on-Chip Modeling,” 6th ACM/IEEE International Symposium on Networks-on-Chip (NOCS12), Lyngby, Denmark, May 9-11, 2012.
  • G. Kurian, C. Sun, C.-H. Chen, J. E. Miller, J. Michel, L. Wei, D. A. Antoniadis, L.-S. Peh, L. Kimerling, Vladimir Stojanovic and Anant Agarwal, “Cross-layer Energy and Performance Evaluation of a Nanophotonic Manycore Processor System using Real Application Workloads,” 26th IEEE International Parallel & Distributed Processing Symposium (IPDPS2012), pp. 1117-1130, 2012.
  • J. T. Ryan, L. Wei, J. P Campbell, R. G. Southwick, K. P. Cheung, A. S. Oates, H. –S. P. Wong, and J. Suehle, “When Does a Circuit Really Fail?”, 2011 IEEE International Integrated Reliability Workshop (IRW 2011), paper 3.2, South Lake Tahoe, USA, October 16– 20, 2011.
  • L. Wei and D. A. Antoniadis, “CMOS Device Design and Optimization from a Perspective of Circuit-Level Energy-Delay Optimization,” 2011 IEEE International Electron Devices Meeting (IEDM 2011), paper 15.3, Washington D.C., USA, December 5– 7, 2011.
  • J. T. Ryan, L. Wei, J. P Campbell, R. G. Southwick, K. P. Cheung, A. S. Oates, H. –S. P. Wong, and J. Suehle, “Circuit-Aware Device Reliability Criteria Methodology,” accepted bythe 41th European Solid-State Device Research Conference (ESSDERC 2011), pp. 255– 258, Helsinki, Finland, September 12– 16, 2011.
  • L. Wei, S. Oh, and H. –S. Philip Wong, “Performance Benchmarks for Si, III-V, TFET, and carbon nanotube FET – Re-thinking the Technology Assessment Methodology for Complementary Logic Applications,” 2010 IEEE International Electron Devices Meeting (IEDM 2010), paper 16.2, San Francisco, USA, December 6 – 8, 2010.
  • J. Luo, L. Wei, F. Boeuf, D. Antoniadis, T. Skotnicki, and H.-S. P. Wong, “Device Engineering for Improving SRAM Static Noise Margin,” 2010 International Conference on Solid State Devices and Materials (SSDM 2010), paper C-4-3, Tokyo, Japan, September 22 – 24, 2010.
  • L. Wei, D. Frank, L. Chang, H.-S. P. Wong, “A Non-iterative Compact Model for Carbon Nanotube FETs Incorporating Source Exhaustion Effects,” 2009 IEEE International Electron Devices Meeting (IEDM 2009), paper 37.7, Baltimore, MD, December 6 – 9, 2009.
  • L. Wei, F. Boeuf, D. Antoniadis, T. Skotnicki, H.-S. P. Wong, “Exploration of Device Design Space to Meet Circuit Speed Targeting 22nm and Beyond,” 2009 International Conference on Solid State Devices and Materials (SSDM 2009), paper E.3.2, Sendai, Japan, September 23 – 26, 2009.
  • L. Wei, F. Boeuf, T. Skotnicki, H.-S. P. Wong, “CMOS Technology Roadmap Projection Including Parasitic Effects,” 2009 International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA 2009), pp. 78-79, Hsinchu, Taiwan, April 27 – 29, 2009.
  • L. Wei, D. Frank, L. Chang, H.-S. P. Wong, “An Analytical Model for Intrinsic Carbon Nanotube FETs,” 38th European Solid-State Device Research Conference (ESSDERC 2008), pp.222-225, Edinburgh, United Kingdom, September 15 – 19, 2008.
  • J. Deng, L. Wei, L.-W. Chang, K. Kim, C.-T. Chuang, H.-S. P. Wong, "Extending Technology Roadmap by Selective Device Footprint Scaling and Parasitics Engineering,"2008 International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA 2008), pp. 159-160, Taiwan, April 21 – 23, 2008.
  • L. Wei, J. Deng, H.-S. P. Wong, “1-D and 2-D Devices Performance Comparison including Parasitic Gate Capacitance and Screening Effect,” 2007 IEEE International Electron Devices Meeting (IEDM 2007), pp. 741 – 744, Washington, D. C., December 10-12, 2007.
  • L. Wei, J. Gao, L. Ji, Z. Chen “A New Structure of Low-Noise CMOS Differential Amplifier”, the 6th International Conference on ASIC (ASICON 2005), pp. 360 – 364, vol. 1, Shanghai, October 24 – 27, 2005.

Invited Papers

  • H. Wei, J. Zhang, L. Wei, N. Patil, A. Lin, M. Shulaker, H.-Y. Chen, H. -S. P. Wong and S. Mitra, “Carbon Nanotube Imperfection-Immune Digital VLSI: Frequently Asked Questions Updated,” 2011 International Conference on Computer-Aided Design (ICCAD 2011).
  • H. –S. P. Wong, S. Mitra, D. Akinwande, C. Beasley, Y. Chai, H. –Y. Chen, X. Chen, G. Close, J. Deng, A. Hazeghi, J. Liang, A. Lin, L. S. Liyanage, J. Luo, J. Parker, N. Patil, M. Shulaker, H. Wei, L. Wei, J. Zhang, “Carbon Nanotube Electronics – Materials, Devices, Circuit, Design, Modeling, and Performance Projection,” IEEE International Electron Devices Meeting (IEDM 2011).
  • Z. Zhang, L. Wei, N. Patil, A. Lin, H.-S. P. Wong, and S. Mitra, “Carbon Nanotube Imperfection-Immune Digital VLSI,” invited keynote paper, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2011.
  • L. Wei, H. –S. P. Wong, “A Fully Analytical Compact Model for Carbon Nanotube Field Effect Transistors including Quantum Capacitances and Electrostatic Model,” 2011 Workshop on Compact Modeling (WCM 2011), Boston, USA, Jun 13–16, 2011.
  • X. Chen, A. Lin, L. Wei, N. Patil, H. Wei, H.-Y. Chen, S. Mitra, and H.-S. P. Wong, “Carbon-Based Nanomaterial for Nanoelectronics”, the Electrochemical Society Trans.vol. 35, pp. 259-269, 2011.
  • S. Oh, L. Wei, S. Chong, J. Luo, and H.-S. P. Wong, “Device and Circuit Interactive Design and Optimization Beyond the Conventional Scaling Era,” invited paper, 2010 IEEE International Electron Devices Meeting (IEDM 2010), San Francisco, USA, December 6 – 8, 2010.
  • L. Wei and H.-S. Philip Wong, “Compact Modeling Aided Technology Design and Projection Considering System-Level Performance,” MOS Modeling and Parameter Extraction Working Group MOS-AK/GSA Workshop (MOS-AK/GSA 2009), Baltimore, USA, December 9, 2009.
  • H.-S. P. Wong, L. Wei, S. Oh, A. Lin, J. Deng, S. Chong, K. Akarvardar, “Technology Projection Using Simple Compact Models,” invited plenary paper, 2009 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD 2009), pp. 1 – 8 (2009).
  • H.-S. P. Wong, L. Wei, J. Deng, “The Future of CMOS Scaling – Parasitics Engineering and Device Footprint Scaling,” invited paper, 2008 International Conference on Solid State and Integrated Circuit Technology (ICSICT 2008), pp. 21 – 24, Beijing, China, October 20 – 23, 2008.

Invited Talks and Seminars

  • L. Wei, “Nanoelectronics: Technology Assessment and Projection at the Device, Circuit, and System Level.”

Stanford University, USA (Jan 2009) , Johns Hopkins University, USA (Feb 2009), University of Southern California, USA (Mar 2009), University of California San Diego, USA (Mar 2009), University of California Riverside, USA (Mar 2009), Carnegie Mellon University, USA (Mar 2009), Shanghai Jiaotong University, China (Apr 2009), University of California Berkeley, USA (Apr 2009)

  • L. Wei, “Device and Circuit Interactive Design.”

Pennsylvania State University, USA (Nov 2011), Semiconductor Manufacturing International Corporation, China, (Jan 2012), Chinese University of Hong Kong, Hong Kong (Jan 2012), Altera Corporation, USA (Feb 2012), Cornell University, USA (Mar 2012), University of Toronto, Canada (Apr 2012), IBM Semiconductor Research and Development Center, USA (May 2012), Qualcomm Research Center, USA (May 2012), University of Waterloo, Canada (Jul 2012), University of Houston, USA (Aug 2012).

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