Deep Reinforcement Learning to Perform Error Rate Aware Qubit Routing and Circuit Optimization

IQC Seminar - Alexander George-Kennedy, Georgia Tech

Protecting quantum information against noise is a widespread goal in quantum computation. In addition to implementing quantum error correcting codes, classical pre-processing steps of circuit optimization and qubit routing can greatly increase the fidelity of the result of a quantum computation. Prior work has shown that neural networks and/or reinforcement learning can be used to discover quantum error correcting codes, perform qubit routing optimized for circuit depth, and find optimal points to insert dynamical decoupling pulse sequences in a quantum circuit. We extend prior work by creating a deep reinforcement learning directed transpiler. We treat the problem of qubit routing and circuit optimization together, and can regard it as a single-player “game,” where the objective is minimizing the output circuit's estimated noise, subject to the connectivity constraints of the architecture. The “moves” in this game available to the transpiler are selecting the qubit layout, introducing SWAP gates subject to architecture constraints, and rewriting the circuit according to equivalency rules (such as introducing dynamical decoupling sequences, or simply optimizing away repeated self-adjoint gates). We train a transpiler for a specific quantum device, in our experiments, each of the available 5-qubit IBM devices, crucially including the reported error rates per gate per qubit per device as part of the transpiler training data. Running the transpilers on a series of random circuits across different devices, we compare the transpiler output circuits with IBM's transpiler outputs. We find an average improvement of 17% reduction in output error rate compared to the IBM transpiler. This is an improvement on prior work that also uses a neural network as a noise-indicating objective function, but with no explicit loading of device error rates, a different vectorization of circuits, and a greedy circuit rewrite policy. Our work is ongoing, as we intend to extend the transpiler's capability in the vein of prior work to construct error correcting codes during optimization.

Add event to calendar